Question:
DESIGN AN UP DOWN COUNTER TO COUNT FROM 0 TO 9 AND 9 TO 0 CONTINUOUSLY WITH A 1.5 SECOND DELAY BETWEEN EACH COUNT AND DISPLAY THE COUNT AT ONE OF THE OUTPUT PORTS. SHOW THE DELAY CALCULATIONS.
Solution:
#ORG 7000H
MVI A,00H //initialize register A=0
INCREMENT: MVI B,00H //load register B as counter
DSPLAY1: OUT PORT1 //display counter value at address port1
LXI H,F422H //initialize HL register pair as delay counter1
LOOP1: DCX H //decrement delay counter1
MOV A,L // load value of register L in register A
ORA H // check delay counter is zero or not
JNZ LOOP1// if delay counter is not equal to zero then jump to loop1
INR B //increment counter
MOV A,B //[B]=>[A]
CPI 09H // compare A with 9
JNZ DSPLAY1 //if A!=9 continue to increase counter
DSPLAY2: MOV A,B //[B]=>[A]
OUT PORT1 //display counter value at port1
LXI H,F422 // initialize register pair HL as delay counter2
LOOP2: DCX H //decrement delay counter2
MOV A,L //[L]=>[A]
ORA H //check HL=0 or not by ORing H &L
JNZ LOOP2 //if delay counter2!=0, jump to LOOP2
DCR B //decrement counter
JNZ DSPLAY2 //if counter!=0 continue to decrease the counter
OUT PORT1 //display counter value at address PORT1
HLT //end of program
DELAY CALCULATION:
Let's take clock frequency be 1MHz
so, Time Period= 1/f
=1/10^6
=1 micro sec
During increment of the counter
Time delay in LOOP1
=(6+4+4+10)*10^-6*delay count1
=24 * 10 ^-6 *delay count1
Total time delay
=(10+10+4+4+7+10)*10^-6 + time delay in LOOP1
=> 1.5= 45 * 10^-6 +24 * 10^-6 + delay count1
=>delay count1=(62498)10
=(F422)16
Similarly the delay count for the decrement of the counter will be same.
0 Comments