OPCODE, BYTES AND EXPLANATION OF ALL MNEMONICS/INSTRUCTIONS OF 8085 PROGRAMMING

 

INSTRUCTION	OPCODE	BYTE	COMMENTS
HLT	76	1	This instruction is used at the end of the program stop processing further execution the program. The contents of the registers are not affected.
NOP	00	1	This instruction instructs the microprocessor to stop and not to perform any operation. The flags are not affected during this operation. It is used to fill the time delay or to delete or insert any instructions during troubleshooting.
OUT  8bit	03	2	This instruction is used to send a data byte from accumulator to output device. For example-  OUT 01H
IN 8 bit	DB	2	This instruction works as an input. It accepts the data bytes received from an input device and loads it in the accumulator.
MVI R,8 bit	Opcode is different for different registers	2	This instruction means move 8 bit data immediately to the register R. This instruction is used to store 8 bit data directly into the register. For example- MVI B, 40H. This instruction will load 40 H to the register B.
MOV Rd,Rs	Opcode is different for different registers.  Check below	1	This instruction copies data bytes from one register to another register. Here, Rs means source register , from where data bytes are copied and Rd is the destination register, to where the data bytes are copied. Note that while writing the instruction, destination register is written first. For example- MOV B,C. Here the source register is C and destination register is B. So, the data bytes of C are copied to the register B. The addressing mode is indirect.
MOV R,M	Opcode is different for different registers. Check below	1	This instruction copies data bytes from memory to register. For example- MOV A,M.  Here, the data bytes from memory location is copied to accumulator. The memory location is specified by HL register pair.
MOV M,R	Opcode is given below	1	This instruction copies the data bytes from register to memory location. For example- MOV M,A copies data bytes from accumulator to memory location.
LXI Rp,16 bit	Opcode is different for different registers. Check below	3	This instruction is used to load 16 bit hexadecimal number to register pairs BC, DE or HL. This instruction is analogous to MVI for 16 bit data bytes. For example- LXI H, 2050 H . It loads 2050 H to HL register pair. The second byte is loaded in the low register of the register pair and the third byte is loaded in the high register of the register pair. In the example:20H is loaded in L and 50H is loaded in H.
LDA 16 bit	3A	3	This instruction loads contents from the memory specified by the 16 bit address to accumulator. For example- LDA 2040H loads the contents of memory address 2040H to accumulator. The addressing mode is direct.
STA 16 bit	32	3	This instruction copies the data bytes from accumulator to the memory address specified by the 16 bit memory address. For example- STA 2040H will load the contents of accumulator to the memory address 2040H
LDAX Rp	Opcode is different for different registers	1	This instruction copies the data bytes from memory location specified by the register pair to the accumulator. For example- LDAX B loads data bytes from the memory location specified by the register pair BC to the accumulator. The addressing mode is indirect.
STAX Rp	Opcode is different for different registers	1	This instruction copies the data bytes from the accumulator to the memory location specified by the register pair. For example- STAX B loads data bytes from accumulator to the memory address specified by the register pair BC.
LHLD 16bit	2A	3	This instruction is used to load HL register pair with the contents of the memory location specified by the 16 bit address.
ADD R	Opcode is different for different registers. check below	1	This instruction is used to add the contents of register R to the contents of the accumulator. For example: ADD B adds the contents of register B to the contents of the accumulator.
ADI 8 bit	C6	2	This instruction adds 8 bit data bytes to the accumulator directly. For example: ADD 42H adds 42H to the contents of accumulator.
ADD M	86	1	This instruction is used to add the contents of the memory location specified by register pair HL to the accumulator.
SUB R	Opcode is different for different registers	1	This instruction is used to subtract the contents of register R to the contents of the accumulator. For example: SUB B subtracts the contents of B from the accumulator and stores the result in the accumulator.
SUI 8 bit	D6	2	This instruction is used to subtract 8 bit data directly from the accumulator. For example: SUI 30H subtracts 30H from the accumulator and  store the result in the accumulator.
SUB M	96	1	This instruction is used to subtract the contents of memory address specified by the HL register pair from the accumulator and stores the result in the accumulator.
INR R	Different for different registers. Check below	1	This instruction is used to increment the contents of register R by 1. For example: INR B will increment the contents of register B by 1. It doesn’t affect the flags.
INR M	34	1	This instruction is used to increment the contents of memory address specified by HL register pair. It doesn’t affect the flags.
DCR R	Different for different registers. Check below	1	This instruction is used to decrement the contents of register R by 1. For example: DCR B will decrement the contents of register B by 1. It doesn’t affect the flags.
DCR M	35	1	This instruction is used to decrement the contents of memory address specified by HL register pair. It doesn’t affect the flags.
INX Rp	Different for different registers. Check below	1	This instruction is used to increment the contents of register pair by 1. It doesn’t affect the flags.
DCX Rp	Different for different registers. Check below	1	This instruction is used to decrement the contents of register pair by 1. It doesn’t affect the flags.
ANA R	Different for different registers. Check below	1	This instruction is used to logically AND  the contents of register to the contents of accumulator. ANA B logically ANDs the contents of B to the contents of accumulator.
ANI 8bit	E6	2	This instruction is used to logically AND 8 bit data directly with the accumulator. For example- ANI 32H will logically AD 32H with the contents of accumulator and saves the result in the accumulator.
ANA M	A6	1	This instruction is used to logically AND the contents of the memory address specified by the HL register pair with the contents of the accumulator.
ORA R	Check below	1	This instruction is used to logically OR the contents of register R with the contents of the accumulator and stores the result in the accumulator. For example-ORA B will logically OR the contents of B with the contents of the accumulator.
ORI 8bit	F6	2	This instruction is used to logically OR 8 bit data with the accumulator and the result is stored in the accumulator. For example- ORI 20 H will logically OR 20 H with the contents of the accumulator.
ORA M	B6	1	This instruction is used to logically OR the contents of the memory address specified by the HL register pair with the contents of accumulator.
XRA R	Check below	1	This instruction is used to exclusive OR the contents of register R with the contents of accumulator and store the result in the accumulator. For example: XRA B will exclusive OR the contents of register B with the contents of accumulator.
XRI 8bit	EE	2	This instruction is used to exclusive OR 8 bit data bytes directly with the accumulator and stores the contents in the accumulator. For example-XRI 10H will exclusive OR 10H with the contents of accumulator.
XRA M	AE	1	This instruction is used to exclusive OR the contents of memory address specified by the HL register pair with the contents of accumulator.
CMP R	Different for different registers. Check below	1	This instruction is used to compare the contents of accumulator with the contents of the register for greater than, less than or equal. For example: CMP B will check whether the contents of accumulator is greater than, equal to or less than the register.
CMA R	2F	1	This instruction is used to complement the binary instruction of register R. For example if register R contains 1001 then it is complemented to 0110
CPI 8bit	FE	3	This instruction is used to compare the 8 bit data with the contents of accumulator. For example: CPI 40H will compare 40 H with the contents of accumulator.
JMP 16bit	C3	3	This instruction is used to change the program sequence to the 16 bit address. It is used in unconditional jump. For example- JMP 2000H will jump the program sequence to 2000H from it’s original address.
JZ 16 bit	CA	3	This instruction is used to change the program sequence to the 16 bit address if the zero flag is set. This is a conditional jump instruction.
JNZ 16bit	C2	3	This instruction is used to change the program sequence if the zero flag is reset to the 16 bit address. This is a conditional jump instruction.
JNC 16bit	D2	3	This instruction is used to change the program sequence to the 16 bit address if the carry flag is reset. This is a conditional jump statement.
JC 16 bit	DA	3	This instruction is used to change the program sequence to the 16 bit address if the carry flag is set. This is a conditional jump instruction.
RLC	07	1	This instruction is used to rotate accumulator left. All bits are shifted towards left. D7 bit becomes zero and carry flag is affected according to D7 bit.
RAL	17	1	This instruction is used to shift all the bits towards left. D7bit becomes carry and carry flag becomes D0.
RRC	0F	1	This instruction is used to shift all the bits towards right. D0 become D7 and carry flag is set according to D0.
RAR	1F	1	This instruction is used to shift all the bits towards right. Bit D0 becomes carry and carry becomes bit D7.

 

 

INSTRUCTION	OPCODE
MVI A,DATA	3E
MVI B,DATA	06
MVI C,DATA	0E
MVI D,DATA	16
MVI E,DATA	1E
MVI H,DATA	26
MVI L,DATA	2E
MVI M,DATA	36
MOV A,A	7F
MOV A,B	78
MOV A,C	79
MOV A,D	7A
MOV A,E	7B
MOV A,H	7C
MOV A,L	7D
MOV A,M	7E
MOV B,A	47
MOV B,B	40
MOV B,C	41
MOV B,D	42
MOV B,E	43
MOV B,H	44
MOV B,L	45
MOV B,M	46
MOV C,A	4F
MOV C,B	48
MOV C,C	49
MOV C,D	4A
MOV C,E	4B
MOV C,H	4C
MOV C,L	4D
MOV C,M	4E
MOV D,A	57
MOV D,B	50
MOV D,C	51
MOV D,D	52
MOV D,E	53
MOV D,H	54
MOV D,L	55
MOV D,M	56
MOV E,A	5F
MOV E,B	58
MOV E,C	59
MOV E,D	5A
MOV E,E	5B
MOV E,H	5C
MOV E,L	5D
MOV E,M	5E
MOV H,A	67
MOV H,B	60
MOV H,C	61
MOV H,D	62
MOV H,E	63
MOV H,H	64
MOV H,L	65
MOV H,M	66
MOV L,A	6F
MOV L,B	68
MOV L,C	69
MOV L,D	6A
MOV L,E	6B
MOV L,H	6C
MOV L,L	6D
MOV L,M	6E
MOV M,A	77
MOV M,B	70
MOV M,C	71
MOV M,D	72
MOV M,E	73
MOV M,H	74
MOV M,L	75
LXI B	01
LXI D	11
LXI H	21
LXI SP	31
LDAX B	0A
LDAX D	1A
STAX B	02
STAX D	12
ADD A	87
ADD B	80
ADD C	81
ADD D	82
ADD E	83
ADD H	84
ADD L	85
ADD M	86
SUB A	97
SUB B	90
SUB C	91
SUB D	92
SUB E	93
SUB H	94
SUB L	95
INR A	3C
INR B	04
INR C	0C
INR D	14
INR E	1C
INR H	24
INR L	2C
INR M	34
INX B	03
INX D	13
INX H	23
INX SP	33
DCR A	3D
DCR B	05
DCR C	0D
DCR D	15
DCR E	1D
DCR H	25
DCR L	2D
DCR M	35
DCX B	0B
DCX D	1B
DCX H	2B
DCX SP	3B
ANA A	A7
ANA B	A0
ANA C	A1
ANA D	A2
ANA E	A3
ANA H	A4
ANA L	A5
ANA M	A6
ORA A	B7
ORA B	B0
ORA C	B1
ORA D	B2
ORA E	B3
ORA H	B4
ORA L	B5
ORA M	B6
XRA A	AF
XRA B	A8
XRA C	A9
XRA D	AA
XRA E	AB
XRA H	AC
XRA L	AD
XRA M	AE
CMP A	BF
CMP B	B8
CMP C	B9
CMP D	BA
CMP E	BB
CMP H	BC
CMP L	BD
CMP M	BD